Emeritus Solutions Ltd

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PDP-8 on an FPGA

Our PDP-8 on an FPGA implementation represents an exemplar both of our execution skills and of the innovative aproaches we can offer to customer problems, such as obsolescence management. Eur Ing Dr Bishop's paper PDP-8 on an FPGA : A Case Study in Obsolescence Management presented at the Component Obsolescence Group (COG) quarterly meeting on 24 September 2008 focuses first on system and software obsolescence and on how this can be mitigated for both new and legacy software. Then, the feasibility of reimplementing the hardware elements of a system to preserve "the system in being" are demonstrated using the PDP-8 on an FPGA as an exemplar. The feasibility not only of re-implementing "any" computer system or digital logic, but also the potential for risk reduction provided by using JTAG to implement targeted, custom instrumentation within the design is demonstrated. And, of course, these JTAG based techniques are equally applicable to new systems and designs.

An earlier version of this paper PDP-8/E on an FPGA : A CaseStudy in Obsolescence which was presented at the MAE Show on 26 September 2006 additionally provides a broader review of obsolescence and a more detailed consideration of contemporary perspectives on software obsolescence management and legacy systems. Using the re-implementation of a classic 1960's minicomputer on an FPGA as an exemplar, the implementation of powerful HCI capabilities on a host PC and the negligible infrastructure required to realise them was described and demonstrated. Specifically, a diskless Digital PDP-8/E was demonstrated as a system on a chip with a PC hosting a superset of the original blinkenlites and switches console.

The PDP-8

The PDP-8 minicomputer was designed and built by the Digital Equipment Corporation (DEC) from 1965 to ~1980. The PDP-8 was the first mass market mini-computer, with lifetime sales of ~50,000. A 12 bit machine it's linear address space of 4 k words ensured it's rapid obsolescence, the DEC PDP-11 16 bit machine rendering it substantially obsolete in 1970. Nonetheless, the PDP-8 was implemented using four generations of technology: Germanium transistors (Straight 8), SSI (PDP-8/I/L), MSI (PDP-8/E/F/M) and LSI (PDP-8/A). Additionally, the PDP-8 possesses two attributes which have contributed to continuing interest in it's architecture and implementations. Firstly, it is a very simple machine and therefore well suited to educational purposes. Secondly, detailed documentation of it's architecture together with copies of it's diagnostics are available in the public domain.

The PDP-8 FAQ maintained by Doug Jones provides an exelent starting point for further reading

The PDP-8 Summary of Models and Options describes the PDP-8 models in greater detail

David Gesswein's site provides examples of and access to serviceable PDP-8's, together with a comprehensive collection of PDP-8 links

The classic source for documentation and binaries is of course www.BitSavers.org


The PDP-8 model selected for implementation was the 8/E, pictured at top left (courtesy of David Gesswein - www.pdp8.net), was chosen as it substantially represents the mature PDP-8 architecture and as comprehensive diagnostics are available on the web.

The primary demonstration was to validate the use of JTAG in user mode to peek and poke Block RAM (BRAM), VHDL / FPGA logic & registers and virtual peripherals (FIFOs) on the Xilinx Spartan 3 FPGA. A brassboard demonstration of this technology was then used to support the PDP-8 implementation. This technology is of, course, an extremely powerful tool permitting inexpensive, non-intrusive monitoring and control of FPGA logic.

The secondary demonstration was of course of the PDP-8/E on an FPGA. The functionality selected for implementation corresponds to a basic PDP-8/E, without either extended memory (4k words are provided by BRAM) or the extended instruction set implemented by the KE8-E (primarily hardware accelerators for MUL and DIV). This functionality was validated by execution of the 8/E's basic diagnostics (MAINDEC-8E-D0AB-PB to MAINDEC-8E-D0JB-PB). Execution with a minor state transition rate of 5MHz runs ~2.5 faster than a "real" 8/E. As the design is presently slugged by a clock enable signal, speeding it up by a factor of 10 to 50MHz is nominally straightforward. This demonstration does of course provide a System-on-a-Chip capability which with the user mode JTAG logic occupies about "100k" of a (small) "200k" Spartan 3 FPGA. While this SOC is neither particularly fast nor compact, the IDE8 IDE does nonetheless provide comprehensive debug capabilities.

The MAE 2006 version of the paper PDP-8/E on an FPGA : A CaseStudy in Obsolescence contains additional photographs, screen shots and diagrams of the PDP-8/E.